1. Field of the Invention
The present invention relates to a sequential controller applied to the field of ordinary life or various industrial fields including mechanical and process plants for implementing the sequential control for various actuating devices, and more particularly to a sequential controller with the ability of an answer-back checking which operates in consideration of operation time of each controlled device when input expected values at two consecutive control steps are different.
2. Description of the Prior Art
In the field of ordinary life and in various industrial fields, there are widely used sequential controllers which control the operation of actuating devices, such as motors, solenoids, electromagnetic valves and cylinders, through preprogrammed logical operations for the detected values of controlled variables such as positions, levels, pressures and temperatures.
An example of conventional sequential controllers is shown in block diagram in FIG. 1. The sequence controller consists of a central processing unit (will be termed simply "CPU" hereinafter) 1 which controls each section of the controller and has a memory for storing the control sequence, an input unit 2 which receives signals from sensing devices in the form of relay contacts and limit switches, an input table 3 which stores the expected input signal pattern, an answer-back timer 4 which counts an answer-back time, an input check unit 5 which compares the input signals with the signal pattern in the input table 3 in accordance with the outputs of the CPU 1, input unit 2, input table 3 and answer-back timer 4, a step advance unit 6 which issues the current step number to the input table 3 and output table 7 (will be explained next) in response to the step advance signal provided by the input check unit 5, an output table 7 which is accessed by the CPU 1 and step advance unit 6 to release a prerecorded output pattern, an output unit 8 which produces output signals for controlling the operation of the actuating devices in accordance with the outputs of the output table 7 and CPU 1, and an alarm output unit 9 which produces an alarm signal based on the outputs of the CPU 1 and input check unit 5.
The operation of the foregoing system arrangement will be described. This sequential controller operates in compliance with a certain control procedure for the intended sequence control programmed in a step table (not shown). FIG. 2 is a detailed logic circuit diagram of the input check unit 5 in the sequential controller, and FIG. 3 is a flowchart showing control procedure of the input unit 5. The following describes the operation of the conventional sequential controller with reference to FIGS. 2 and 3.
Initially in step ST1, the output pattern of signals to be produced for lst output 1 through n-th output is read out of the output table 7 via the output unit 8 to the 1st output through n-th output. For example, the 1st through n-th outputs are given 1, 0, 0, . . . , 0 in step ST1. Then, the answer-back timer 4 starts counting time in step ST2, and subsequently signals from 1st input through n-th input are entered to the input check unit 5 via the input unit 2 in step ST3 as shown in FIG. 3. In step ST4, the expected values of these input signals received through the 1st through n-th inputs are compared with the input signal pattern which is set in the input table 3. Namely, for the above example, step 1 of sequence control tests whether or not input values of the 1st through n-th inputs as shown by the above step pattern are equal to 1, 0, 0, . . . , 0. If all input signals are consistent with the input pattern at the currently executed step in the input table 3 (will be termed "current step input expected values" hereinafter) as tested in step ST5, the control step is advanced in step ST6. If, on the other hand, step ST5 has detected inconsistency between any input signal and the corresponding input expected value, expiration of the answer-back timer 4 is tested in steps ST7 and ST8. Unless the timer 4 has expired, the operations following the input signal reading, i.e., steps ST3, ST4 and ST5 are repeated. If the steps ST7 and ST8 have detected the expiration of the answer-back timer 4, the input check unit 5 issues an alarm signal to the outside via the alarm output unit 9 in step ST9 so as to inform the abnormality of the control operation or the external device.
In case input expected values are different between two consecutive control steps, it is necessary to allow a certain suspension time before the end of the operation determined by the answer-back timer 4 in consideration that the pertinent controlled device is slow in operation and needs more time to respond to the activation signal. An example of this case is shown in the portion of 2nd input indicated by symbol Pa in FIG. 4, which is a timing chart showing the transition of the input 2 in the control step table. In another case where the current step input expected values are equal in two consecutive control steps, it is not necessary to provide an actuation signal for the controlled device for changing the state of the controlled device between the two control steps. In this case, however, execution of the sole answer-back checking mentioned above cannot detect the abnormal operation of the device, i.e., erroneous transition of the signal to "1" which ought to be "0", as shown in the portion of 2nd input indicated by symbol Pb in FIG. 4.
The conventional sequence controller arranged as described above has a problem in which the answer-back checking takes place irrespective of whether current step input expected values of one input are equal or unequal between two consecutive control steps.
An example of the foregoing prior art sequential controller is described in Japanese Patent Publication Laid-open No. 57-52907.